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electronics semiconductor division features wide frequency range e 0.01 hz to 300 khz wide supply voltage range e 4.5v to 20v dtl/ttl/ecl logic compatibility fsk demodulation with carrier-detector wide dynamic range e 2 mv to 3 v rms adjustable tracking range e 1% to 80% excellent temperature stability e 20 ppm/ c typical applications fsk demodulation data synchronization tone decoding fm detection carrier detection description the rc2211 is a monolithic phase-locked loop (pll) system especially designed for data communications. it is particularly well-suited for fsk modem applications, and operates over a wide frequency range of 0.01 hz to 300 khz. it can accommodate analog signals between 2 mv and 3v, and can interface with conventional dtl, ttl and ecl logic families. the circuit consists of a basic pll for tracking an input signal frequency within the passband, a quadrature phase detector which provides carrier detection, and an fsk voltage comparator which provides fsk demodulation. external components are used to indepen- dently set carrier frequency, bandwidth and output delay. block diagram 65-2211-01 f -detector loop filter vco f f fsk input preamp data filter fsk data output fsk comparator lock detector outputs lock detector comparator lock detector filter f -detector rc2211 fsk demodulator/tone decoder rev. 1.0.1 this document was created with framemaker 4 0 4
product specification rc2211 2 description of circuit controls signal input (pin 2) the input signal is ac coupled to this terminal. the internal impedance at pin 2 is 20 k w . recommended input signal level is in the range of 10 mv rms to 3 v rms . quadrature phase detector output, q (pin 3) this is the high impedance output of the quadrature phase detector, and is internally connected to the input of lock detector voltage comparator. in tone detection applications, pin 3 is connected to ground through a parallel combination of r d and c d (see figure 1) to eliminate chatter at the lock detector outputs. if this tone detector section is not used, pin 3 can be left open circuited. lock detector output, q (pin 5) the output at pin 5 is at a high state when the pll is out of lock and goes to a low or conducting state when the pll is locked. it is an open collector output and requires a pull-up resistor, r l , to +v s for proper operation. in the low state it can sink up to 5 ma of load current. lock detector complement, q (pin 6) the output at pin 6 is the logic complement of the lock detector output at pin 5. this output is also an open collector type stage which can sink 5 ma of load current in the low or on state. fsk data output (pin 7) this output is an open collector stage which requires a pull-up resistor, r l , to +v s for proper operation. it can sink 5 ma of load current. when decoding fsk signals the fsk data output will switch to a high or off state for low input frequency, and will switch to a low or on state for high input frequency. if no input signal is present, the logic state at pin 7 is indeterminate. fsk comparator input (pin 8) this is the high impedance input to the fsk voltage comparator. normally, an fsk post detection or data tlter is connected between this terminal and the pll phase detector output (pin 11). this data tlter is formed by r f and c f of figure 1. the threshold voltage of the comparator is set by the internal reference voltage, v r , available at pin 10. reference bypass (pin 9) this pin can have an optional 0.1, m f capacitor connected to the ground. reference voltage, v r (pin 10) this pin is internally biased at the reference voltage level, v r ; v r = +v s /2 e 650 mv. the dc voltage level at this pin forms an internal reference for the voltage levels at pin 3, 8, 11 and 12. pin 10 must be bypassed to ground with a 0.1 m f capacitor. figure 1. generalized circuit connection for fsk and tone detection 65-2211-02 0.1 f internal reference fsk comparator fsk output +v s r l r b c f r f (12) vco (14) (13) r 0 c 0 quad f -detector (3) c d r d 100k to 470k input signal 0.1 f input preamp loop f -detector c 1 r 1 100k 510k lock detector comparator q q lock detector outputs (6) (5) (10) (8) (1) (7) (2) (11) f f
rc2211 product specification 3 loop phase detector output (pin 11) this terminal provides a high impedance output for the loop phase detector. the pll loop tlter is formed by r1 and c1 connected to pin 11 (see figure 1). with no input signal, or with no phase error within the pll, the dc level at pin 11 is very nearly equal to v r . the peak voltage swing available at the phase detector output is equal to v r . vco control input (pin 12) vco free running frequency is determined by external timing resistor, r0, connected from this terminal to ground. the vco free running frequency, f 0 is given by: where c 0 is the timing capacitor across pins 13 and 14. for optimum temperature stability r 0 must be in the range of 10 k w to 100 k w (see typical performance characteristics). this terminal is a low impedance point, and is internally biased at a dc level equal to v r . the maximum timing cur- rent drawn from pin 12 must be limited to 3 ma for proper operation of the circuit. vco timing capacitor (pins 13 and 14) vco frequency is inversely proportional to the external tim- ing capacitor, c 0 , connected across these terminals. c 0 must be non-polarized, and in the range of 200 pf to 10 m f. vco frequency adjustment vco can be tne tuned by connecting a potentiometer, rx, in series with r 0 at pin 12 (see figure 2). vco free-running frequency, f 0 the rc2211 does not have a separate vco output terminal. instead, the vco outputs are internally connected to the phase detector sections of the circuit. however, for set-up or adjustment purposes, the vco freerunning frequency can be measured at pin 3 (with c d disconnected) with no input and with pin 2 shorted to pin 10. design equations see figure 1 for detnitions of components. 1. vco center frequency, f 0 : f 0 hz () 1 r 0 c 0 ------------- = f 0 hz () 1 r 0 c 0 ------------- = 2. internal reference voltage, v r (measured at pin 10) 3. loop lowpass filter time constant, t t = r 1 c 1 4. loop dampening, z : 5. loop tracking bandwidth, d f/f 0 : 6. fsk data filter time constant, t f : t f = r f c f 7. loop phase detector conversion gain, k f (k f is the differential dc voltage across pins 10 and 11, per unit of phase error at phase-detector input): 8. vco conversion gain, k 0 is the amount of change in vco frequency per unit of dc voltage change at pin 11: 9. total loop gain, k t : k t (in radians per second per volt)= 2 p k f k0 = 10. peak phase detector current, i a : v r +v s 2 ---------- ? ?? -650 mv = z c 0 c 1 ------ ? ? ?? 1 4 -- - ? ?? = 65-2211-03 tracking bandwidth d f d f f ll f 1 f 0 f 2 f lh d f/f o = r0/r1 k f in volts per radian () 2 e () v r () p --------------------------- - = k0 in hertz per volt () 1 e c 0 r 1 v r --------------------- = 4 c 0 r 1 ------------- i a ma () v r 25 ------- =
product specification rc2211 4 pin assignments absolute maximum ratings thermal characteristics parameter min max unit supply voltage -20 +20 v input signal level 3 v rms storage temperature range -65 +150 c operating temperature range rm2211d -55 +125 c rv2211n -25 +85 c rc2211n -0 +70 c junction temperature pdip +125 c cerdip +175 c lead soldering temperature (60 sec.) +300 c max. p d t a <50 c pdip 468 mw cerdip 1042 mw parameter 14 lead plastic dip 14 lead ceramic dip therm. res q jc ?60 c/w therm. res. q ja 160 c/w 120 c/w for t a > 50 c derate at 6.5 mw/ c 8.33 mw/ c 65-2211-04 +v s input lock detector filter gnd fsk data output q q timing capacitor timing capacitor timing resistor loop f -detector fsk comparator input reference bypass reference voltage output 14 13 12 11 10 9 8 1 2 3 4 5 6 7
rc2211 product specification 5 electrical characteristics (test conditions +v s = +12v, t a +25 c, r0 = 30 k w , c0 = 0.033 m f. see figure 1 for component designations.) notes: 1. guaranteed by design. 2. individual applications may need special circuitry to function at <12v. 3. sample tested. rv/rm2211 rc2211 parameters test conditlons min typ max min typ max units general supply voltage 2 4.5 20 4.5 20 v supply current r 0 3 10 k w 4.0 9.0 5.0 11 ma oscillator frequency accuracy deviation from f 0 = 1/r 0 c 0 1.0 3.0 1.0 % frequency stability 1 temperature coefficient r 1 = 20 50 20 ppm/ c power supply rejection +v s = 12 1v +v s = 5 0.5v 0.05 0.2 0.5 0.2 0.05 %/v %/v upper frequency limit r 0 = 8.2 k w , c 0 = 400 pf 100 300 300 khz lowest practical operating frequency 1 r 0 = 2 m w , c 0 = 50 m f 0.01 0.01 hz timing resistor, r 0 operating range 5.0 2000 5.0 2000 k w recommended range 15 100 15 100 k w loop phase detector peak output current measured at pin 11 150 200 300 100 200 300 m a output offset current 1.0 2.0 m a output impedance 1.0 1.0 m w maximum swing ref. to pin 10 4.0 5.0 4.0 5.0 v quadrature phase detector peak output current 3 measured at pin 3 100 150 150 m a output impedance 1.0 1.0 m w maximum swing 11 11 v p-p input preamp input impedance measured at pin 2 20 20 k w input signal voltage required to cause limiting 3 2.0 10 2.0 mv rms voltage comparator input impedance measured at pins 3 & 8 2.0 2.0 m w input bias current 100 100 na voltage gain 1 r l = 5.1 k w 55 70 55 70 db output voltage low i c = 3ma 300 300 mv output leakage current v 0 = 12v 0.01 0.01 m a internal reference voltage level measured at pin 10 4.9 5.3 5.7 4.75 5.3 5.85 v output impedance 100 100 w
product specification rc2211 6 applications fsk decoding figure 2 shows the basic circuit connection for fsk decod- ing. with reference to figures 1 and 2, the functions of external components are detned as follows: r 0 and c 0 set the pll center frequency, r 1 sets the system bandwidth, and c 1 sets the loop tlter time constant and the loop damping factor. c f and r f form a one pole post-detection tlter for the fsk data output. the resistor r b (510 k w ) from pin 7 to pin 8 introduces positive feedback across fsk comparator to facilitate rapid transition between output logic states. recommended component values for some of the most commonly used fsk bauds are given in table 1. figure 2. circuit connectbn for fsk decoding table 1. recommended component values for commonly used fsk bands (see circuit of figure 2) design instructions the circuit of figure 2 can be tailored for any fsk decoding application by the choice of tve key circuit components: r 0 , r 1 , c 0 , c 1 and c f . for a given set of fsk mark and space frequencies, f 1 and f 2 , these parameters can be calculated as follows: fsk band component values 300 baud c 0 = 0.039 m f, c f = 0.005 m f f 1 = 1070 hz c 1 = 0.01 m f, r 0 = 18 k w f 2 = 1270 hz r 1 = 100 k w 300 baud c 0 = 0.022 m f, c f = 0.005 m f f 1 = 2025 hz c 1 = 0.0047 m f, r 0 = 18 k w f 2 = 2225 hz r 1 = 200 k w 1200 baud c 0 = 0.027 m f, c f = 0.0022 m f f 1 = 1200 hz c 1 = 0.01 m f, r 0 = 18 k w f 2 = 2200 hz r 1 = 30 k w 1 2 3 4 5 6 7 14 13 12 11 10 9 8 rc2211 65-2211-05 c 0 vco fine tune r 0 r x 5k r 1 c 1 0.1 f r f 100k 510k c f fsk data output 5.1k +v s 0.1 f 0.1 f +v s fsk input r l r b 1. calculate pll center frequency, f 0 2. choose a value of timing resistor r 0 to be in the range of 10 k w to 100 k w . this choice is arbitrary. the recom- mended value is r 0 = 20 k w . the tnal value of r 0 ios normally tnetuned with the series potentiometer, r x . 3. calculate value of c 0 from design equation no. 1 or from typical performance characteristics: c 0 = 1/r 0 f 0 4. calculate r 1 to give a d f equal to the markspace deviation: r 1 = r 0 [f 0 /(f 1 - f 2 )] 5. calculate c 1 to set loop damping. (see design equation no. 4) normally, z ? 1/2 is recommended then: c 1 = c 0 /4 for z = 1/2 6. calculate data filter capacitance, c f : for r f = 100 k w , r b = 510 k w , the recommended value of c f is: note: all calculated component values except ro can be rounded off to the nearest standard value, and r0 can be varied to fine-tune center frequency through a series potentiometer, r x (see figure 2). design example 75 baud fsk demodulator with mark space frequencies of 1110/1170 hz: step 1: calculate f 0 : f 0 =(1110+1170)(1/2)= 1140hz step 2: choose r 0 = 20 k w (18 k w txed resistor in series with 5 k w potentiometer) step 3: calculate c 0 from vco frequency vs. timing capacitor: c 9 = 0.044 m f step 4: calculate r 1 : r 1 = r 0 (1140/60) = 380 k w step 5: calculate c 1 : c 1 = c 0 /4 = 0.011 m f note: all values except r 0 can be rounded off to nearest standard value. ff 0 f 1 f 2 + 2 ----------------- - = c f in m f () 3 baud rate ------------------------ - =
rc2211 product specification 7 fsk decoding with carrier detector the lock detector section of the rc2211 can be used as a carrier detector option for fsk decoding. the recommended circuit connection for this application is shown in figure 3. the open-collector lock detector output, pin 6, is shorted to the data output (pin 7). thus, the data output will be disabled at low state, until there is a carrier within the detection band of the pll, and the pin 6 output goes high to enable the data output. figure 3. external connections for fsk demodulation with carrier detector capability the minimum value of the lock detector tlter capacitance c d is inversely proportional to the capture range, d f c . this is the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. it is further limited by c 1 . for most applications, d f c < d f/2. for r d = 470 k w , the approximate minimum value of c d can be determined by: c d ( m f) 3 16/capture range in hz with values of c d that are too small, chatter can be observed on the lock detector output as an incoming signal frequency approaches the capture bandwidth. excessively large values of c d will slow the response time of the lock detector output. tone detection figure 4 shows the generalized circuit connection for tone detection. the logic outputs, q and q at pins 5 and 6 are normally at high and low logic states, respectively. when a tone is present within the detection band of the pll, the logic state at these outputs becomes reversed to the duration of the input tone. each logic output can sink 5 ma of load current. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 rc2211 65-2211-06 c 0 vco fine tune r 0 r x 5k r 1 c 1 0.1 f r f 100k 510k c f data output 5.1k +v s c o 470k 0.1 f 0.1 f +v s fsk inputs note: data output is "low" when no carrier is present. figure 4. circuit connection for tone detection both logic outputs at pins 5 and 6 are open-collector type stages, and require external pull-up resistors r l1 and r l2 as shown in figure 4. with reference to figures 1 and 4, the function of the external circuit components can be explained as follows: r 0 and c 0 set vco center frequency, r 1 sets the detection bandwidth, c 1 sets the lowpass-loop tlter time constant and the loop dampening factor, and r l1 and r l2 are the respec- tive pull-up resistors for the q and q logic outputs. design instructions the circuit of figure 4 can be optimized for any tone-detec- tion application by the choice of tve key circuit components: r 0 , r 1 , c 0 , c 1 and c d . for a given input tone frequency, f s , these parameters are calculated as follows: 1. choose r 0 to be in the range of 15 k w to 100 k w . this choice is arbitrary. 2. calculate c 0 to set center frequency, f 0 equal to f s : c 0 = 1/r 0 f s . 3. calculate r 1 to set bandwidth d f (see design equa- tion no. 5): r 1 = r 0 (f 0 / d f). note: the total detection bandwidth covers the frequency range of f 0 d f. 4. calculate value of c 1 for a given loop damping factor: c 1 =c 0 /16 z 2 normally z = 1/2 is optimum for most tone detector applications, giving c 1 = 0.25 c0. increasing c 1 improves the out-of-band signal rejection, but increases the pll capture time. 5. calculate value of tlter capacitor c d . to avoid chatter at the logic output, with r d = 470 w , c d must be: c d ( m f) 3 (16/capture range in hz) increasing c d slows the logic output response time. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 rc2211 65-2211-07 c 0 vco fine tune r 0 r x 5k r 1 c 1 0.1 f logic output +v s c o 470k 0.1 f 0.1 f +v s fsk inputs q r l1 r l2 +v s q logic outputs
product specification rc2211 8 design examples tone detector with a detection band of 1 khz 20 hz: step 1: choose r 0 = 20 k w (18 k w in series with 5 k w potentiometer) . step 2: choose c 0 for f 0 = 1 khz: c 0 = 0.05 m f. step 3: calculate r 1 : r 1 = (r 0 ) (1000/20) = 1 m w . step 4: calculate c 1 : for z = 1/2, c 1 = 0.25 m f, c 0 = 0.013 m f. step 5: calculate c d : c d = 16/38 = 0.42 m f. step 6: fine tune the center frequency with the 5 k w potentiometer. r x . linear fm detection the rc2211 can be used as a linear fm detector for a wide range of analog communications and telemetry applications. the recommended circuit connection for the application is shown in figure 5. the demodulated output is taken from the loop phase detector output (pin 11), through a post detection tlter made up of r f and c f , and an external buffer ampliter. this buffer ampliter is necessary because of the high impedance output at pin 11. normally, a non-inverting unity gain op amp can be used as a buffer ampliter, as shown in figure 5. the fm detector gain, i.e., the output voltage change per unit of fm deviation, can be given as: v out = r 1 v r /100 r 0 volts/% deviation where v r is the internal reference voltage. for the choice of external components r 1 , r 0 , c 0 , c 1 and c f , see the section on design instructions. figure 5. linear fm detector using rc2211 and an external op amp 65-2211-08 (12) (11) r 1 r f 100k r 0 c 1 c f +v s demodulated ouput (14) (13) (2) fm input c k c o 0.1 f 0.1 f +v s 0.1 f rc2211 (8) (1) (10) (4)
rc2211 product specification 9 typical performance characteristics figure 6. supply current vs. supply voltage figure 7. timing resistor with timing (logic outputs open circuited) capacitor vs. vco frequency figure 8. timing capacitor with timing figure 9. center frequency drift vs. temperature resistor vs. vco frequency figure 10. vco frequency vs. supply voltage 6 410 81216 14 20 18 +v s (v) i s (ma) 20 15 10 5 0 65-2211-09 22 24 r 0 = 5 k w r 0 = 10 k w r 0 > 100 k w r 0 = 5 k w? r 0 = 10 k w? r 0 = 20 k w? r 0 = 40 k w? r 0 = 80 k w? r 0 = 160 k w 65-2211-10 100 1k f o (hz) c0 ( f) 10 1.0 0.1 10k c 0 = 0.001 f c 0 = 0.0033 f c 0 = 0.01 f c 0 = 0.033 f c 0 = 0.1 f c 0 = 0.33 f 65-2211-11 01 f o (hz) r0 (k w ) 1k 100 10 10 r 0 = 10 k w? ? r 0 = 50 k w? ? r 0 = 500 k w? ? r 0 = 1 m w? ? 1 m w 500 k w 50 k w 10 k w 65-2211-12 -50 +25 -25 +75 +50 +100 temperature ( ? c) normalized center frequency drift (% of f o ) 1.0 0.5 0 -0.5 -1.0 +125 0 curve 1 2 3 4 5 r0 5k 10k 30k 100k 300k 1.02 1.01 1.00 0.99 0.98 0.97 f o = 1 khz r 10 r0 4 6 8 10 12 14 16 18 20 22 24 65-2211-13 normalized frequency -v s (v)
product specification rc2211 10 schematic diagram 65-2211-14 +v s r2 20k q4 q17 q18 input (2) reference voltage output q47 q48 r12 18k r11 18k from vco b b q81 q82 q83 q84 q79 q80 q88 d87 lock detector filter q86 q85 d86 q83 q84 lock detector outputs (5) q42 (6) q38 lock detector comparator quadature phase detector input pramplifier and limitter d56 d57 r3 20k r18 2k q97 q109 d96 q95 a c0 timing capacitor a d108 r19 2k b b q103 d101 r37 8k r0 timing resistor d89 q92 (4) gnd voltage controlled oscillator (12) q60 a a from vco q68 q62 d111 d72 d73 q65 q64 q71 q74 loop f -detector output (11) (8) q23 q20 q25 q27 (7) fsk data output d24 fsk comparator q68 d67 loop phase detector q61 intenal voltage reference (3) d85 (14) (13) fsk comparator input (1)
rc2211 product specification 11 notes:
product specification rc2211 12 notes:
rc2211 product specification 13 notes:
product specification rc2211 14 mechanical dimensions 14-lead ceramic dip package a .200 5.08 symbol inches min. max. min. max. millimeters notes b1 .014 .023 .36 .58 .065 1.65 b2 .045 1.14 c1 .008 .015 .20 .38 e .220 .310 5.59 7.87 e .100 bsc 2.54 bsc l .125 .200 3.18 5.08 .015 .060 .38 1.52 .005 .13 3 6 8 4 8 2 4 5, 9 ea .300 bsc 7.62 bsc 7 q s1 90 ? 105 ? 90 ? 105 ? a d .785 19.94 notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. index area: a notch or a pin one identification mark shall be located adjacent to pin one. the manufacturer's identification shall not be used as pin one identification mark. the minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 7, 8 and 14 only. dimension "q" shall be measured from the seating plane to the base plane. this dimension allows for off-center lid, meniscus and glass overrun. the basic pin spacing is .100 (2.54mm) between centerlines. each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 14. applies to all four corners (leads number 1, 7, 8, and 14). "ea" shall be measured at the center of the lead bends or at the centerline of the leads when " a " is 90 ? . all leads ?increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. twelve spaces. note 1 d e s1 8 14 7 1 b2 q a e b1 l ea c1 a
rc2211 product specification 15 mechanical dimensions (continued) 14-lead plastic dip package d b1 e b e1 a1 a l 7 8 14 1 e eb c d1 a .210 5.33 symbol inches min. max. min. max. millimeters notes a1 .015 .38 .022 .56 b .014 .36 .195 4.95 a2 .115 2.93 b1 .045 .070 1.14 1.78 d .725 .795 18.42 20.19 .300 .325 7.62 8.26 e eb .430 10.92 .115 .200 2.92 5.08 4 2 e .100 bsc 2.54 bsc 2 l 14 14 5 n .240 .280 6.10 7.11 e1 c .008 .015 .20 .38 d1 .005 .13 notes: 1. 2. 3. 4. 5. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e1" do not include mold flashing. mold flash or protrusions shall not exceed .010 inch (0.25mm). terminal numbers are shown for reference only. "c" dimension does not include solder finish thickness. symbol "n" is the maximum number of terminals.
product specification rc2211 12/95 0.0m stock#ds20002211 raytheon company 1995 the information contained in this data sheet has been carefully compiled; however, it shall not by implication or otherwise bec ome part of the terms and conditions of any subsequent sale. raytheon?s liability shall be determined solely by its standard terms and conditio ns of sale. no representation as to application or use or that the circuits are either licensed or free from patent infringement is intende d or implied. raytheon reserves the right to change the circuitry and any other data at any time without notice and assumes no liability for errors. life support policy: raytheon?s products are not designed for use in life support applications, wherein a failure or malfunction of the component ca n reasonably be expected to result in personal injury. the user of raytheon components in life support applications assumes all risk of such use and indemnites raytheon company against all damages raytheon electronics semiconductor division 350 ellis street mountain view ca 94043 415 968 9211 fax 415 966 7742 ordering information notes: /883b suffix denotes mil-std-883, par 1.2.1 compliant devices n = 14-lead plastic dip d = 14-lead ceramic dip part number package operating temperature range rc2211n n 0 c to +70 c rv2211n n -25 c to +85 c rm2211d d -55 c to +125 c rm2211d/883b d -55 c to +125 c

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